(1) Field of the Invention
This invention relates generally to ring oscillator circuits and relates more particularly to a ring oscillator with almost constant delay time even if the operating voltage drops down.
(2) Description of the Prior Art
Ring oscillators are used for a variety of purposes. Usually ring oscillators are used as an internally generated clocking source, or as a stage in a more complex system such as a voltage controlled oscillator (VCO) or a phase locked loop (PLL). They are often used to issue a refresh command for e.g. DRAM memory devices.
For many applications, e.g. memory circuit design, a circuit having a constant delay is very important.
FIG. 1 prior art shows a circuit diagram of a 5-stage CMOS inverter chain ring oscillator. Normally the number of stages is an odd number (3, 5, 7, or . . . ) with the output of the cascade fed back to the input of the inverter chain. An oscillator provides an output at a specific frequency with no input signal required.
All these five inverter stages IN1 to IN5 have an identical circuit configuration. The first stage IN1 is equipped with a CMOS inverter INV1 comprising a PMOS transistor PI1 and an NMOS transistor NI1. Furthermore a PMOS transistor PN1 and a NMOS transistor NN1 provide a current source for this inverter stage IN1. The other stages IN2 to IN5 are equipped identically.
The output of the last stage IN5 is the input INP1 of the first inverter INV1. This input INP1 is connected to the gates of the CMOS transistors PI1 and NI1. The output OUT1 of the first inverter INV1 is connected to the drain of PMOS transistor PI1, to the drain of NMOS transistor NI1 and the input of the second inverter stage IN2.
The PMOS transistor PI1 has its source connected to the operating voltage VCC via PMOS transistor PN1. The NMOS transistor NI1 has its source connected to VSS voltage via NMOS transistor NN1.
The current I1 from voltage VCC to VSS through PMOS transistor P1, resistor R1 and NMOS transistor N1 follows the equation
            I      ⁢                          ⁢      1        =                  VP        -        VN                    R        ⁢                                  ⁢        1              ,wherein VP is the voltage at the drain of transistor P1 and VN is the voltage at the drain of transistor N1. The current I1 is mirrored to the first inverter stage via the current mirrors P1/PN1 and N1/NN1. Accordingly current I1 is mirrored to the other inverter stages as well. In case the operating voltage VCC drops down, the voltage difference VP-VN becomes very small. Especially in the light of new semiconductor technologies (most fabs moved for the most advanced ICs from 0.18 micron to 0.13 microns) the typical operating voltages used to turn the transistors on and off have been reduced from e.g. 2.5 volts to 1.8 volts, the circuits are becoming more sensitive in case of variations during the manufacturing process or in case of changing temperatures. Even if all devices are within manufacturing specifications PMOS devices have a higher speed than normal if the threshold voltage is lower than normal and vice versa the speed of NMOS devices is lower than normal if their threshold voltage is higher than normal.
This means that in case the threshold voltage of the PMOS or NMOS devices is higher than normal the difference of voltages VP and VN will be smaller. Vice versa the difference of voltages VP and VN will be larger if the threshold voltage of the PMOS or NMOS devices is lower than normal. Furthermore the semiconductor devices and resistor R1 depend in their performance upon changes of temperature. Therefore the current I1 and, by mirroring, the currents through the inverter stages IN1 to IN5 will be not constant but vary dependent upon the temperature and upon manufacturing process variations. Thus the delay time of the prior art ring oscillator will vary upon different temperatures and different manufacturing process parameters, even if these parameters are within specifications and even if the operating voltage VCC is regulated.
Since voltage VP>VN and voltage VP equalsVP=VCC−|VTHP1|,wherein |VTHP1| is the threshold voltage of P1, and voltageVN≅VTHN1,wherein VTHN1 is the threshold voltage of N1, the following equation is valid:VCC=|VTHP1|+VTHN1+I1×R1.Accordingly the ring oscillator shown in FIG. 1 prior art can only work precisely if the voltage difference I1×R1 is much larger than the sum of the threshold voltages |VTHP1|+VTHN1 
There are known patents to control the delay time of ring oscillators:
U.S. Pat. No. 6,813,210 to Okamoto et al. teaches a semiconductor memory device including a refresh timer for determining a refresh cycle of self-refresh operation. The refresh timer includes a voltage regulator, a ring oscillator and a counter. The voltage regulator generates a bias voltage having positive temperature characteristics. The ring oscillator varies an oscillation cycle of a pulse signal according to the bias voltage. The counter counts a prescribed number of pulse signals and generates a refresh signal for executing refresh operation. The semiconductor memory device thus varies the refresh cycle according to a temperature change, and executes refresh operation with an appropriate refresh cycle.
U.S. Pat. No. (6,188,293 to Miyagi et al.) discloses a low-power consumption integrated ring oscillator capable of stable operation throughout a wide voltage range without undergoing a large frequency change including a first constant voltage generating circuit having an enhancement mode P-MOS transistor and a depletion mode N-MOS transistor and a second constant voltage generating circuit having a depletion mode N-MOS transistor and an enhancement mode N-MOS transistor. A first constant voltage generated by the first constant voltage circuit is applied to a gate electrode of a P-MOS transistor of transmission gates connected between respective cascaded inverters of the ring oscillator. A second constant voltage generated by the second constant voltage generating circuit is connected to the gate electrode of an N-MOS transistor of the transmission gates. By this construction, current consumption is reduced and battery lifetime can be increased. The boosting circuit for writing and erasing an EEPROM circuit may be formed with the low power ring oscillator.
U.S. Pat. No. (5,898,343 to Morgan) discloses a refresh circuit of a memory device including a ring oscillator with a frequency stabilizing circuit. The frequency stabilizing circuit produces compensated voltage signals in response to changes in supply voltage and temperature to modify the conductances of field-effect transistors of the frequency stabilizing circuit to compensate the conductive path of the discharge current of a capacitor from the ring oscillator in order to stabilize the oscillation frequency.